1. Field of the Invention
The present invention relates to a solid-state imaging device, which is capable of extending a dynamic range, and a method of driving the solid-state imaging device; and a camera using such solid-state imaging device and a method of driving the camera. Particularly, the present invention relates to a solid-state imaging device, such as a CMOS image sensor, in which a pixel includes a charge converting portion for converting a charge generated by photoelectric conversion into a pixel signal, and a method of driving the solid-state imaging device; and a camera using such solid-state imaging device and a method of driving the camera.
The term “CMOS image sensor” used herein refers to as an image sensor produced by the application of or partially using the CMOS process. The solid-state imaging device may be formed of a single chip or a plurality of chips.
2. Description of the Related Art
CMOS image sensors and CCD image sensors have been known as solid-state imaging devices. In the solid-state imaging device, each pixel is configured to convert incident light into charge by photoelectric conversion and accumulate the charge, while reading out the accumulated charge as signal charge. The solid-state imaging device of this kind is typically provided with a blooming-preventing structure. The blooming-preventing structure is responsible for preventing the generation of blooming such that charge to be photo-electrically converted is overflowed and limited to a certain overflow level corresponding to the maximum amount of charge accumulated. However, if the maximum amount of charge accumulated is defined, it will restrict a dynamic range. In other words, output signal levels corresponding to the respective inputs of large amount of light that generates charge exceeding the overflow level are always equal to one another, thereby causing a loss of light-intensity information.
In order to extend the dynamic range, there is proposed a method in which an overflow level is changed from a low level to a high level in the middle of a charge accumulation period for each pixel and a Knee characteristic is then given to a relationship between light intensity and output signal. Japanese Unexamined Patent Application Publication No. 10-248035 (JP 10-248035 A) and Japanese Examined Patent Application Publication No. 4-32589 (JP 4-32589 B) disclose MOS solid-state imaging devices on which the method of changing overflow levels is applied. JP 10-248035 A proposes a method of raising an overflow level by ternary drive of readout voltage, while JP 4-32589 B proposes a method of raising an overflow level in the vertical direction by changing the voltage of a p-type semiconductor well region on a n-type substrate.
FIG. 1 shows an equivalent circuit used in an example of a unit pixel of a related-art CMOS solid-state imaging device. A unit pixel 100 includes a photodiode (PD) 101 provided as a photoelectric converting portion, and four MOS transistors including a transfer transistor 102, a reset transistor 103, an amplification transistor 104, and a selection transistor 105. The cathode of the photodiode 101 is connected to a gate of the amplification transistor 104 via the transfer transistor 102. A node electrically connected with the gate of the amplification transistor 104 is referred to as a floating diffusion portion FD. The floating diffusion portion FD includes the drain region of the transfer transistor 102.
The transfer transistor 102 is connected between the cathode of the photodiode 101 and the floating diffusion portion FD. In addition, a transfer pulse φTRG is applied to a gate of the transfer transistor 102 via a transfer wiring 107. The reset transistor 103 has a drain connected to a pixel power source line (Vdd) 109 and a source connected to the floating diffusion portion FD. In addition, a reset pulse φRST is applied to a gate of the transfer transistor 103 via a reset wiring 108.
The amplification transistor 104 has a gate connected to the floating diffusion portion FD, a drain connected to the pixel power source 109, and a source connected to a drain of the selection transistor 105. The selection transistor 105 has a source connected to a vertical signal line 106. In addition, a selection pulse φSEL is applied to a gate of the selection transistor 105 via a selection wiring 110.
In the pixel 100, prior to readout of charge accumulated in the photodiode 101, the reset transistor 103 is turned on to reset the floating diffusion portion FD to the voltage of the pixel power source. Then, the potential of the floating diffusion portion FD after the reset is read out to the vertical signal line 106. After that, the transfer transistor 102 is turned on to transfer signal charge accumulated in the photodiode 101 to the floating diffusion portion FD. Subsequently, the signal charge is converted into a pixel signal and then read out to the vertical signal line 106. The previous reset potential and the pixel signal are subjected to noise reduction through CDS processing in a CDS processing circuit of a column processing circuit and then outputted as a pixel signal.